那位老兄给点建议设！！！


 

在属于比较基本的东东啊，在baidu google上一搜就能搜到例程，一般的教科书上也会有介绍的．



library IEEE; 

use IEEE.std_logic_1164.all; 

use IEEE.std_logic_arith.all; 

use IEEE.std_logic_signed.all; 



entity myclock is 

port ( 

clk_1khz : in std_logic; 

reset : in std_logic; 

second : out std_logic_vector (5 downto 0); 

minite : out std_logic_vector (5 downto 0); 

hour : out std_logic_vector (3 downto 0) 

); 

end myclock; 



architecture rtl of myclock is 



begin 

process (clk_1khz, reset) 



variable ms : std_logic_vector(9 downto 0); 

variable mysecond, myminite : std_logic_vector(5 downto 0); 

variable myhour : std_logic_vector(3 downto 0); 



begin 



if reset = '1' then 

mysecond := "000000"; 

myminite := "000000"; 

myhour := "0000"; 

ms := (others =>'0'); 

elsif clk_1khz'event and clk_1khz = '1' then 

-- count ms to 1000 

ms :=ms+1; 

if ms = "1111101000" then 

ms := (others => '0'); 

mysecond := mysecond+1; 

if mysecond = "111100" then 

mysecond := "000000"; 

myminite := myminite + 1; 

if myminite = "111100" then 

myminite := "000000"; 

myhour := myhour + 1; 

if myhour = "1100" then 

myhour := "0000"; 

end if; 

end if; 

end if; 

end if; 

end if; 



second <= mysecond; 

minite <= myminite; 

hour <= myhour; 

end process; 

end architecture;